Motorola MTX Series Programmer's Reference Manual page 60

TDIS RAEN PCI Command
x 0 Read
Read Line
0 1 Read
Read Line
x Read Multiple
1 1 Read
Read Line
x Read Multiple
Upon completion of a prefetched read transaction, any residual read data
left within the FIFO will be invalidated (discarded). The Raven does not
have a mechanism for snooping the PPC bus for transactions associated
with the prefetched read data within it's FIFO, therefore caution should be
exercised when using the prefetch option within coherent memory space.
The user should select a PCI command type, a transaction size and a TDIS
bit setting that minimizes wasted PPC bus bandwidth due to unnecessary
prefetching. For example, there will be no unnecessary prefetching if the
user always performs a burst read of 4 cache lines and the TDIS option is
enabled. If the user wishes to perform very long burst transactions, then the
TDIS option should be disabled since the benefits of a long uninterrupted
transaction far exceed the penalty of a few unused prefetch cycles.
The PPC master will never perform prefetch reads beyond the address
range mapped within the PCI slave map decoders. As an example, assume
Raven has been programmed to respond to PCI address range $10000000
through $1001FFFF with an offset of $2000. The PPC master will perform
its last read on the PPC bus at cache line address $3001FFFC or word
address $3001FFF8.
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Initial Read Size Continuation
1 cache line PCI received data
and
FRAME*
asserted
4 cache lines FIFO <= 1cache
line
4 cache lines PCI received data
and
FRAME*
asserted
Functional Description
Subsequent
Read Size
1 cache line
2 cache lines
2 cache lines
2-7
2