1PosSSI/Analog
6.7 CPU /Master Stop and RESET State
6.7
CPU/Master Stop and RESET State
Behavior at CPU-Master-STOP
Behavior at CPU-Master-STOP
Due to power-off of the CPU/DP master
•
or
Due to power-off of the IM 151/ IM 151 FO
•
or
Due to failure of DP transmission
•
or
Due to change from RUN to STOP
•
Exiting the CPU-Master-STOP Status
Exiting the CPU-Master-STOP Status
At power-on of the CPU/DP master
•
or
At power-on of the IM 151/ IM 151 FO
•
or
After failure of the DP transmission
•
or
After a change from STOP to RUN
•
296
Response of the 1PosSSI/Analog
The current run is stopped.
•
–
Analog output QV+ is set to 0 V
–
Digital output:
if the direction is assigned parameters for the DO
function, the digital output OUT=0 is set
Feedback bit POS_ERR = 0
•
Feedback bit POS_DONE = 1
•
Response of the 1PosSSI/Analog
The feedback interface of the 1PosSSI/Analog remains
•
current.
The axis remains synchronized, and the actual value is
•
current.
The following changed values remain valid:
•
–
Voltage for rapid feed
–
Voltage for creep feed
–
Acceleration (T
)
acc
–
Deceleration T
dec
–
Switch-off and switchover difference
–
The path difference for the monitoring of the direction of
rotation remains valid.
An initiated JOB 10: Latch function remains active.
•
The feedback bit selected with JOB 15 is current.
•
Operating Instructions, 05/2007, A5E00124871-04
ET 200S Positioning