Extended Feature Enable Register (Efer); Figure 2. Extended Feature Enable Register (Efer); Table 10. Extended Feature Enable Register (Efer) Definition - AMD -K6-2/450 - MHz Processor Application Note

Embedded AMD-K6™ Processors BIOS Design Guide

Extended Feature Enable Register (EFER)

63
Reserved
Symbol Description
SCE System Call Extension
Figure 2. Extended Feature Enable Register (EFER) (Models 7 and 8/[7:0])
Table 10. Extended Feature Enable Register (EFER) Definition (Models 7 and 8/[7:0])
Bit Description
Reserved
63–1
0
System Call Extension (SCE)
Notes:
1. The AMD-K6E processor Model 7 provides the SCE bit in the EFER register, but this bit does not affect processor operation because the
SYSCALL and SYSRET instructions and the STAR register are not supported in this models.
18
Preliminary Information
The Extended Feature Enable Register (EFER) contains the
control bits that enable the extended features of the AMD-K6
processor. Figure 2 shows the format of the EFER register, and
Table 10 defines the function of each bit of the EFER register.
The EFER register is MSR C000_0080h.
Bit
0
R/W
R
1
R/W
Function
Writing a 1 to any reserved bit causes a general protection
fault to occur. All reserved bits are always read as 0.
SCE must be set to 1 to enable the usage of the SYSCALL and
SYSRET instructions.
Model 7 and Model 8/[7:0] Registers
23913A/0—November 2000
1 0
S
C
E