Pci Interface; Pci Map Decoders - Motorola MVME2600 Series Reference Manual

The bus timer starts ticking at the beginning of an address transfer (TS*
asserted), and if the address transfer is not terminated (AACK* asserted)
before the time-out period has passed, the Raven will assert the MATO bit
in the MPC Error Status Register, latch the MPC address in the MPC Error
Address Register, and then immediately assert AACK*.
The MATO bit may be configured to generate an interrupt or a machine
check through the MEREN register.
The timer is disabled if the transfer is intended for PCI. PCI bound
transfers will be timed by the PCI master.

PCI Interface

The Raven PCI Interface is designed to connect directly to a PCI Local Bus
compliant I/O bus.
The PCI interface may operate at any clock speed up to 33 MHz. The
PCLK input must be externally synchronized with the MCLK input, and
the frequency of the PCLK input must be exactly half the frequency of the
MCLK input.

PCI Map Decoders

The Raven contains four programmable decoders which provide windows
into the MPC bus from the PCI bus. The most significant 16 bits of the PCI
address is compared with the address range of each map decoder, and if the
address falls within the specified range, the access is passed on to the MPC
bus. For each map, there is an independent set of attributes. These
attributes are used to enable read accesses, enable write accesses, enable
write posting, and define the MPC bus transfer characteristics. Each map
decoder also includes a programmable 16-bit address offset. The offset is
added to the 16 most significant bits of the PCI address, and the result is
used as the MPC address. This offset allows devices to reside at any MPC
address, independent of the PCI address map.
All Raven address decoders are prioritized so that programming multiple
decoders to respond to the same address will not be a problem. When the
PCI address falls into the range of more than one decoder, only the highest
priority one will respond. The decoders are prioritized as shown below.
Functional Description
2-11
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