Mpc Write Posting - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2

MPC Write Posting

2-8
released. If the EXT01 pin is sampled in the low state, the MPC register
file will start at address $FEFE0000. If the EXT01 pin is sampled in the
high state, the MPC register file will start at address $FEFF0000. All
references to the MPC register file within this specification will assume a
base address of FEFF0000. All Raven registers are described in detail later
in this chapter.
The Raven includes four programmable decoders which control accesses
from the MPC bus to the PCI bus. These decoders provide a window into
the PCI bus from the MPC bus. The most significant 16 bits of the MPC
address are compared with the address range of each map decoder, and if
the address falls within the specified range, the access is passed on to PCI.
For each map, there is an associated set of attributes. These attributes are
used to enable read accesses, enable write accesses, enable write posting,
and define the PCI transfer characteristics. Each map decoder also includes
a programmable 16-bit address offset. The offset is added to the 16 most
significant bits of the MPC address, and the result is used as the PCI
address. This offset allows PCI devices to reside at any PCI address,
independent of the MPC address map.
Care should be taken to assure that all programmable decoders decode
unique address ranges. Overlapping address ranges will lead to undefined
operation.
The MPC write FIFO stores up to eight data beats in any combination of
single- and burst transactions. If write posting is enabled, Raven stores the
data necessary to complete an MPC write transfer to the PCI bus and
immediately acknowledges the transaction on the MPC bus. This frees the
MPC bus from waiting for the potentially long PCI arbitration and transfer.
The MPC bus may be used for more useful work while the Raven manages
the completion of the write posted transaction on PCI.
If the write post FIFO is full, any other accesses to the Raven are delayed
(AACK* will not be asserted) until there is room in the FIFO to store the
complete transaction.