Table 1-6. Raven Mpc Register Values For Prep Memory Map - Motorola MVME2600 Series Reference Manual

control bit is set then this address range maps to ROM/FLASH Bank
B.
5. This range can be mapped to the VMEbus by programming the
Universe ASIC accordingly.
6. The only method to generate a PCI Interrupt Acknowledge cycle
(8259 IACK) is to perform a read access to the Raven's PIACK
register at 0xFEFF0030.
The following table shows the programmed values for the associated
Raven MPC registers for the processor PREP memory map.

Table 1-6. Raven MPC Register Values for PREP Memory Map

Address
FEFF 0040
FEFF 0044
FEFF 0048
FEFF 004C
FEFF 0050
FEFF 0054
FEFF 0058
FEFF 005C
PCI Configuration Access
PCI Configuration accesses are accomplished via the CONFIG_ADD and
CONFIG_DAT registers. These two registers are implemented by the
Raven ASIC. In the CHRP memory map example, the CONFIG_ADD and
CONFIG_DAT registers are located at 0xFE000CF8 and 0xFE000CFC,
respectively. With the PREP memory map, the CONFIG_ADD register
and the CONFIG_DAT register are located at 0x80000CF8 and
0x80000CFC, respectively.
Register Name
MSADD0
MSOFF0 & MSATT0
MSADD1
MSOFF1 & MSATT1
MSADD2
MSOFF2 & MSATT2
MSADD3
MSOFF3 & MSATT3
Programming Model
Register Value
C000 FCFF
4000 00C2
0000 0000
0000 0002
0000 0000
0000 0002
8000 BFFF
8000 00C0
1
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