Motorola MVME2600 Series Reference Manual page 278

Numerics
8259 compatibility 2-54
8259 interrupts 5-4
8259 mode 2-82
A
A0-A31 3-5
abbreviations, acronyms, and terms to know
GL-1
Access Timing (DRAM) 3-8, 3-9,
Access Timing (ROM) 3-11
address modification for little endian trans-
fers 2-18
Address Pipelining 3-6
Address Transfers 3-12
Application-Specific
(ASIC) 1-1
architectural diagram for the Universe
architectural notes 2-82
architectural overview 4-2
architecture 2-52
ARTRY_ 3-12
assertion, definition 1-2
asterisk (*) 1-2
B
Base Module Feature Register
Base Module Status Register (BMSR)
big to little endian data swap
big-endian 1-3
big-endian mode 5-12
binary number 1-2
Bit Descriptions 3-32
3-10
Integrated Circuit
4-3
1-37
1-38
2-17
block diagram 2-4
block diagram description
board
documentation A-3
Bus Interface (60x) 3-12
byte ordering 1-3
byte, definition 1-3
C
Cache Coherency 3-12
CHRP compliant memory map
CHRP memory map example
CLK FREQUENCY 3-38
CLK Frequency Register
Clock Frequency 3-38
Column Address 3-45
CONFIG_ADDRESS 2-49
Control Bit Descriptions
control bit, definition 1-3
conventions, manual 1-2
CPU Configuration Register
CPU Control Register 1-33
CSR Accesses 3-23
CSR Architecture 3-24
CSR Base Address 3-24
CSR Reads and Writes 3-24
CSR's readability 2-53
current task priority level
cycles originating from PCI
D
Data Path Diagram 3-62
Data Path Mapping 3-63
Index
2-57
2-7
1-10
3-38
3-32
1-36
2-82
2-18
IN-1