Motorola MVME2600 Series Reference Manual page 10

Performance ........................................................................................................3-6
Four-beat Reads/Writes ...............................................................................3-6
Single-beat Reads/Writes ............................................................................3-7
DRAM Speeds .............................................................................................3-7
ROM/Flash Speeds ....................................................................................3-11
PowerPC 60x Bus Interface..............................................................................3-12
Responding to Address Transfers..............................................................3-12
Completing Data Transfers........................................................................3-12
Cache Coherency .......................................................................................3-12
Cache Coherency Restrictions...................................................................3-13
L2 Cache Support ......................................................................................3-13
ECC...................................................................................................................3-13
Cycle Types ...............................................................................................3-13
Error Reporting..........................................................................................3-13
Error Logging ............................................................................................3-15
DRAM Tester....................................................................................................3-15
ROM/Flash Interface ........................................................................................3-16
Refresh/Scrub....................................................................................................3-20
Blocks A and/or B Present, Blocks C and D Not Present .........................3-20
Blocks A and/or B Present, Blocks C and/or D present ............................3-21
DRAM Arbitration............................................................................................3-21
Chip Defaults ....................................................................................................3-22
External Register Set ........................................................................................3-22
CSR Accesses ...................................................................................................3-23
Programming Model ................................................................................................3-24
CSR Architecture..............................................................................................3-24
Register Summary.............................................................................................3-29
Detailed Register Bit Descriptions ...................................................................3-32
Vendor/Device Register ............................................................................3-33
Revision ID/ General Control Register .....................................................3-34
DRAM Attributes Register ........................................................................3-36
DRAM Base Register ................................................................................3-37
CLK Frequency Register ...........................................................................3-38
ECC Control Register ................................................................................3-38
Error Logger Register ................................................................................3-41
Error_Address Register .............................................................................3-43
Scrub/Refresh Register ..............................................................................3-43
Refresh/Scrub Address Register ................................................................3-44
ROM A Base/Size Register .......................................................................3-45
ROM B Base/Size Register .......................................................................3-48
DRAM Tester Control Registers ...............................................................3-51
32-Bit Counter ...........................................................................................3-51
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