Pci Memory Maps; Table 1-7. Pci Chrp Memory Map - Motorola MVME2600 Series Reference Manual

Board Description and Memory Maps
1

PCI Memory Maps

PCI Address
Start
0000 0000 top_dram
4000 0000 EFFF FFFF
F000 0000 F7FF FFFF
F800 0000 F8FE FFFF
F8FF 0000 F8FF FFFF
F900 0000 F9FE FFFF
F9FF 0000 F9FF FFFF
FA00 0000 FAFE FFFF
FAFF 0000 FAFF FFFF
FB00 0000 FBFE FFFF
FBFF 0000 FBFF FFFF
FC00 0000 FC03 FFFF
1-14
The PCI memory map is controlled by the Raven ASIC and the Universe
ASIC. The Raven ASIC and the Universe ASIC have flexible
programming Map Decoder registers to customize the system to fit many
different applications.
Default PCI Memory Map
After a reset, the Raven ASIC and the Universe ASIC turn all the PCI slave
map decoders off. Software must program the appropriate map decoders
for a specific environment.
PCI CHRP Memory Map
The following table shows a PCI memory map of the MVME2600/2700
series that is CHRP-compatible from the point of view of the PCI local bus.

Table 1-7. PCI CHRP Memory Map

Size
End
dram_size
3G - 256M
128M
16M - 64K
64K
16M - 64K
64K
16M - 64K
64K
16M - 64K
64K
256K
Definition
Onboard ECC DRAM
VMEbus A32/D32 (Super/Program)
VMEbus A32/D16 (Super/Program)
VMEbus A24/D16 (Super/Program)
VMEbus A16/D16 (Super/Program)
VMEbus A24/D32 (Super/Data)
VMEbus A16/D32 (Super/Data)
VMEbus A24/D16 (User/Program)
VMEbus A16/D16 (User/Program)
VMEbus A24/D32 (User/Data)
VMEbus A16/D32 (User/Data)
RavenMPIC
Notes
1
3
3
4
4
4
4
4
4
4
4
1