Bit Ordering Convention; Introduction; Overview; Features - Motorola MVME2600 Series Reference Manual

3Falcon ECC Memory Controller

Introduction

The Falcon DRAM controller ASIC is designed for the MVME2600/2700
family of boards. It is used in sets of two to provide the interface between
the PowerPC 60x bus and a 144-bit ECC-DRAM memory system. It also
provides an interface to ROM/Flash.

Overview

This chapter provides a functional description and programming model for
the Falcon. Most of the information for using the device in a system,
programming it in a system, and testing it is contained here.

Bit Ordering Convention

All Falcon bused signals are named using big-endian bit ordering (bit 0 is
the most significant bit).

Features

DRAM Interface
– Double-bit error detect/Single-bit error correct on 72-bit basis.
– Up to four blocks.
– Programmable base address for each block.
– Two-way interleave factor.
– Built-in Refresh/Scrub.
– Programmable sequencer for fast DRAM tests.
Error Notification for DRAM
– Software programmable Interrupt on Single/Double-Bit Error.
– Error address and Syndrome Log Registers for Error Logging.
Chip Set
3
3-1