Motorola MVME2600 Series Reference Manual page 279

Data Paths 3-61
Data Transfers
decimal number
default PCI memory map
default processor memory map
derc 3-39
Disable Error Correction Control Bit
DMA controller
documentation
double word, definition
DRAM Addressing
DRAM Addressing Examples
DRAM Attributes Register
DRAM Base Register
DRAM Connection Diagram
DRAM Enable Bits
DRAM Size Control Bits
DRAM Speed Control Bits
DRAM Speeds
DRAM Tester
DRAM Tester Control Register
DRAM tester control registers
dynamically changing I/O interrupt configu-
ration
E
ECC Control Register
elog 3-41
embt 3-42
endian conversion
endian issues 5-11
End-of-Interrupt Registers
EOI Register 2-81
Error Address Register
Error Correction
I
Error Correction Codes
N Error Detection
error handling
D
Error Logger Register
E
Error Logging
X
error notification and handling
Error Reporting
IN-2
3-12
1-2
1-14
1-9
3-39
4-7
A-3
1-3
3-58
3-64
3-36
3-37
3-5
3-36
3-36
3-35
3-7
3-15
3-51
3-51
2-81
3-38
2-16
2-78
3-43
3-13
3-59
3-13
2-18
3-41
3-15
5-10
3-14
ERROR_ADDRESS 3-43
ERROR_SYNDROME 3-42
esbt 3-42
escb 3-41
esen 3-41
exceptions 5-8
external interrupt service
External Register Set 3-22,
External Register Set Reads and Writes
External Source Destination Registers
External Source Vector/Priority Registers
2-72
F
Falcon-controlled system registers
false, definition 1-3
Fast Refresh Control Bit 3-35
Feature Reporting Register
Features 3-1
features 2-2
Flash (See ROM/Flash) 3-16
functional description 1-7, 2-5,
G
General Control Register
General Control-Status/Feature Registers
2-25
general information 4-1
General Purpose Registers
generating PCI configuration cycles
generating PCI interrupt acknowledge cycles
2-16
generating PCI memory and I/O cycles
generating PCI special cycles
Global Configuration Register
glossary GL-1
H
half-word, definition 1-3
hexadecimal character 1-2
Computer Group Literature Center Web Site
Index
2-79
3-54
3-24
2-74
1-27
2-65
4-2
3-34
2-41
2-15
2-13
2-15
2-66