Spurious Vector Generation; Interprocessor Interrupts (Ipi); Compatibility - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Spurious Vector Generation

2

Interprocessor Interrupts (IPI)

8259 Compatibility

2-54
Under certain circumstances the RavenMPIC will not have a valid vector
to return to the processor during an interrupt acknowledge cycle. In these
cases the spurious vector from the spurious vector register will be returned.
The following cases would cause a spurious vector fetch.
INT is asserted in response to an externally sourced interrupt which
is activated with level sensitive logic and the asserted level is
negated before the interrupt is acknowledged.
INT is asserted for an interrupt source which is masked using the
mask bit in the Vector-Priority register before the interrupt is
acknowledged.
Processor 0 and 1 can generate interrupts which are targeted for the other
processor or both processors. There are four Interprocessor Interrupts (IPI)
channels. The interrupts are initiated by writing a bit in the IPI dispatch
registers. If subsequent IPIs are initiated before the first is acknowledged,
only one IPI will be generated. The IPI channels deliver interrupts in the
Direct Mode and can be directed to more than one processor.
The RavenMPIC provides a mechanism to support PC-AT compatible
chip sets using the 8259 interrupt controller architecture. After power-on
reset, the RavenMPIC defaults to 8259 pass-through mode. In this mode,
interrupts from external source number 0 (the interrupt signal from the
8259 is connected to this external interrupt source on the RavenMPIC) are
passed directly to processor 0. If the pass-through mode is disabled, the
8259 interrupts are delivered using the priority and distribution
mechanisms of the RavenMPIC.
The RavenMPIC does not interact with the vector fetch from the 8259
interrupt controller.