Motorola MVME2600 Series Reference Manual page 93

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip
2
2-26
MBTx MPC Bus Time-out. This field specifies the MPC bus
time-out length. The time-out length is encoded as
follows:
MBT
00
01
10
11
P64 64-bit PCI Mode Enable. If set, the Raven is connected
to a 64-bit PCI bus. This bit is set if REQ64* is asserted
on the rising edge of RESET*.
MARB MPC Arbiter Enable. If set, the Raven internal MPC
Arbiter is enabled. This bit is set if CPUID is %111 on the
rising edge of RESET*.
MPIC Multi-Processor Interrupt Controller Enable. If set,
the Raven internal MPIC interrupt controller is enabled.
This bit is set if EXT15 is high on the rising edge of
RESET*. If cleared, Raven detected errors will be passed
on to processor 0 INT pin.
MIDx Master ID. This field is encoded as shown below to
indicate who is currently the MPC bus master. When the
internal MPC arbiter is enabled (MARB is set), these bits
are controlled by the internal arbiter. When the internal
arbiter is disabled (MARB is clear) these bits reflect the
status of the CPUID pins. In a multiprocessor
environment, these bits allow software to determine on
which processor it is currently running. The internal MPC
arbiter encodes this field as follows:
Time Out Length
256 sec
64 sec
8 sec
disabled