Dram Base Register - Motorola MVME2600 Series Reference Manual

Table 3-11. Block_A/B/C/D Configurations
ram a/b/c/d Block
siz0-2
SIZE
%100 128MB
%101 256MB
%110 1024MB
%111 0MB

DRAM Base Register

ADDRESS
BIT
NAME
RAM A BASE
OPERATIO
READ/WRITE
N
RESET
0 PL
RAM A/B/C/D BASE These control bits define the base address for
Devices Used Technology
18 - 8Mx8's
144 - 16Mx1's
36 - 16Mx4's
4 - 16Mx36's 64Mb/16Mb
144 - 64Mx1's
- - -
$FEF80018
RAM B BASE RAM C BASE
READ/WRITE
0 PL
their block's DRAM. RAM A/B/C/D BASE bits 0-7/8-
15/16-23/24-31 correspond to PowerPC 60x address bits
0 - 7. For larger DRAM sizes, the lower significant bits of
A/B/C/D BASE are ignored. This means that the block's
base address will always appear at an even multiple of its
size. Note that bit 0 is MSB.
Also note that the combination of RAM_X_BASE and
ram_x_siz should never be programmed such that
DRAM responds at the same address as the CSR,
ROM/Flash, External Register Set, or any other slave on
the PowerPC bus.
Programming Model
Comments
64Mb
16Mb
64Mb
SIMM/DIMM
64Mb
- Reserved
RAM D BASE
READ/WRITE READ/WRITE
0 PL
3
0 PL
3-37