Lm/Sig Status Register - Motorola MVME2600 Series Reference Manual

SET_LM1 Writing a 1 to this bit will set the LM1 status bit.
SET_LM0 Writing a 1 to this bit will set the LM0 status bit.
CLR_SIG1Writing a 1 to this bit will clear the SIG1 status bit.
CLR_SIG0Writing a 1 to this bit will clear the SIG0 status bit.
CLR_LM1 Writing a 1 to this bit will clear the LM1 status bit.
CLR_LM0 Writing a 1 to this bit will clear the LM0 status bit.

LM/SIG Status Register

The LM/SIG Status Register is an 8-bit register located at ISA I/O address
x1001. This register, in conjunction with the LM/SIG Control Register,
provides a method to generate interrupts. The Universe ASIC is
programmed so that this register can be accessed from the VMEbus to
provide a capability to generate software interrupts to the onboard
processor(s) from the VMEbus.
REG
BIT SD7
FIELD EN
SIG1
OPER
RESET 0
EN_SIG1 When the EN_SIG1 bit is set, a LM/SIG Interrupt 1 is
EN_SIG0 When the EN_SIG0 bit is set, a LM/SIG Interrupt 0 is
EN_LM1 When the EN_LM1 bit is set, a LM/SIG Interrupt 1 is
EN_LM0 When the EN_LM0 bit is set, a LM/SIG Interrupt 0 is
LM/SIG Status Register - Offset $1001
SD6 SD5 SD4
EN EN EN
SIG0 LM1 LM0
R/W
0 0
generated if the SIG1 bit is asserted.
generated if the SIG0 bit is asserted.
generated and the LM1 bit is asserted.
generated and the LM0 bit is asserted.
ISA Local Resource Bus
SD3 SD2
SIG1 SIG0
READ-ONLY
0 0 0
1
SD1 SD0
LM1 LM0
0 0
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