Table 1-4. Raven Mpc Register Values For Chrp Memory Map - Motorola MVME2600 Series Reference Manual

4. CHRP requires the starting address for the PCI memory space to be
256MB-aligned.
5. Programmable via Raven ASIC for either contiguous or spread-I/O
mode.
6. The actual size of each ROM/FLASH bank may vary.
7. The first one Mbyte of ROM/FLASH Bank A appears at this range
after a reset if the rom_b_rv control bit is cleared. If the rom_b_rv
control bit is set then this address range maps to ROM/FLASH Bank
B.
8. This range can be mapped to the VMEbus by programming the
Universe ASIC accordingly. The map shown is the recommended
setting which uses the Special PCI Slave Image and two of the four
programmable PCI Slave Images.
9. The only method to generate a PCI Interrupt Acknowledge cycle
(8259 IACK) is to perform a read access to the Raven's PIACK
register at 0xFEFF0030.
The following table shows the programmed values for the assoc- iated
Raven MPC registers for the processor CHRP memory map.

Table 1-4. Raven MPC Register Values for CHRP Memory Map

Address
FEFF 0040
FEFF 0044
FEFF 0048
FEFF 004C
FEFF 0050
FEFF 0054
FEFF 0058
FEFF 005C
Register Name
MSADD0
MSOFF0 & MSATT0
MSADD1
MSOFF1 & MSATT1
MSADD2
MSOFF2 & MSATT2
MSADD3
MSOFF3 & MSATT3
Programming Model
Register Value
4000 FCFF
0000 00C2
FD00 FDFF
0300 00C2
0000 0000
0000 0002
FE00 FE7F
0200 00C0
1
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