Pci I/O Config_Address Register - Motorola MVME2600 Series Reference Manual

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

PCI I/O CONFIG_ADDRESS Register

2
Offset
Bit 3
1
Name
Operation
Reset
LEND = 0
LEND = 1
2-50
3 2 2 2 2 2 2 2 2 2
0 9 8 7 6 5 4 3 2 1
R
$00
MPC[39:32] MPC[47:40]
MPC[31:24] MPC[23:16]
REG Register Number. For PCI Configuration cycles, bits 7
through 2 identify the target double word within the target
function's configuration space. Bits 1 and 0 must always
be zero for a type 0 configuration cycle. These bits are
copied to the PCI AD bus during the address phase on a
Configuration cycle.This field must be all zeros for
Special cycles.
FUN Function Number. For PCI Configuration cycles, bits 10
through 8 identify the function number within the target
physical PCI device. These bits are copied to the PCI AD
bus during the address phase on a Configuration cycle.
This field must be all ones for Special cycles.
DEV Device Number. For PCI Configuration cycles, bits 15
through 11 identify the target physical PCI device
number. Raven does a decode of the Device Number field
to assert the appropriate IDSEL line. Values of $01
through $0a and $1f are illegal entries for the device
number. The Raven will drive all 0's in bit position AD11
through AD31 if a illegal device id is initialized into the
configuration address register. A value of $0B sets PCI
AD bit 11 (IDSEL 11) during the address phase of a
$CF8
2 1 1 1 1 1 1 1 1 1
0 9 8 7 6 5 4 3 2 1
CONFIG_ADDRESS
BUS DEV
R/W R/W
$00 $00
MPC[55:48]
MPC[15:8]
1
0 9 8 7 6 5 4 3 2 1 0
FUN REG
R/W R/W
$0 $00
MPC[63:56]
MPC[7:0]