Motorola MVME2600 Series Reference Manual page 230

PCI Reset Problems Associated with the Initial Version of the Universe Chip
MCG is not sure how many of the Power Up (P/U) Option bits actually get
latched as the Universe manual indicates they should. At least the EN bit
in the LSI0_CTL bit is not latched; in our board, its P/U state is disabled
but is not honored.
The software cannot completely correct this problem, but it can minimize
it. Two methods are presented:
Method 1:
1. Modify the PCI probe code to disable each PCI device prior to
writing its configuration space BS registers. This will prevent the
Universe from being active on the PCI bus while it has a base addr
of 0.
2. Once the Universe has been assigned a valid PCI Base Address,
enable register space access and disable the LSI0 slave image by
clearing the EN bit of the LSI0_CTL register.
Method 2:
The port 92 reset code can be modified to disable the LSI0 image
prior to propagating the reset. This will cause the LSI0 image to
come up disabled.
We at MCG understand that both of these methods are awkward, because
the PCI probe/reset code should not contain any device-specific patches. It
should only need to follow the probing conventions of the PCI
specification. However, the only other option appears to be avoidance of
the LSI0 image altogether.
Tundra engineering describes the problem thus:
"Following are the most recently discovered bugs which will be
addressed in Universe 1.1.
1. LSIO image
Description: After a PCI reset, the LSIO image is still enabled, but the
base, bound, and translation offset changes value.
Workaround: None."
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