Memory Configuration Register (Memcr) - Motorola MVME2600 Series Reference Manual

Board Description and Memory Maps
1

Memory Configuration Register (MEMCR)

REG
BIT
FIELD
OPER
RESET
1-30
The states of the RD[00:31] DRAM data pins, which have weak internal
pull-ups, are latched by the lower Falcon chip at a rising edge of the power-
up reset and stored in this Memory Configuration Register to provide some
information about the system memory. Configuration is accomplished
with external pull-down resistors. This 32-bit read-only Register is defined
as follows:
Memory Configuration Register - $FEF80404
M_FREF Block A/B/C/D Fast Refresh. When this bit is set, it
indicates that a DRAM block requires faster refresh rate.
If any of the four blocks requires faster refresh rate then
the ram ref control bit should be set.
M_SPD[0:1] Memory Speed. This field relays the memory speed
information as follows:
M_SPD[0:1]
0b00
0b01
0b10
0b11
DRAM Speed
70ns
60ns
Reserved
50ns
DRAM Type
Past Page
Fast Page
Reserved
EDO