General Purpose Registers; Pci Registers - Motorola MVME2600 Series Reference Manual

IOM

General Purpose Registers

Address
Bit
0 1 2 3 4 5 6 7 8 9
Name
Operation
Reset
These general purpose read/write registers are provided for inter-process
message passing or general purpose storage. They do not control any
hardware.

PCI Registers

The PCI Configuration Registers are compliant with the configuration
register set described in the PCI Local Bus Specification, Revision 2.0.
The CONFIG_ADDRESS and CONFIG_DATA registers described in
this section are accessed within PCI I/O space.
All write operations to reserved registers will be treated as no-ops. That is,
the access will be completed normally on the bus and the data will be
discarded. Read accesses to reserved or unimplemented registers will be
completed normally and a data value of 0 returned.
The Raven PCI Configuration Register map is shown in Table 2-6. The
Raven PCI I/O Register map is shown in Table 2-7.
PCI I/O Mode. If set, the corresponding MPC slave will
generate PCI I/O cycles using spread addressing as
defined in the section on Generating PCI Memory and I/O
Cycles. When clear, the corresponding MPC slave will
generate PCI I/O cycles using contiguous addressing.
GPREG0 (Upper) - $FEFF0070
GPREG0 (Lower) - $FEFF0074
GPREG1 (Upper) - $FEFF0078
GPREG1 (Lower) - $FEFF007C
1 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7
GPREGx
R/W
$00000000
1 1 2 2 2 2 2 2 2 2
8 9 0 1 2 3 4 5 6 7
Registers
2
2 2 3 3
8 9 0 1
2-41