Motorola MVME2600 Series Reference Manual page 17

Table 3-3. PowerPC 60x Bus to DRAM Access Timing When
Configured for 50ns Hyper Devices ........................................................................ 3-10
Table 3-4. PowerPC 60x Bus to ROM/Flash Access Timing When
Configured for 32/64-bit Devices............................................................................ 3-11
Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing When
Configured for 8-bit Devices ................................................................................... 3-11
Table 3-6. Error Reporting....................................................................................... 3-14
Table 3-7. PowerPC 60x to ROM/Flash Address Mapping with Two
8-bit Devices............................................................................................................ 3-17
Table 3-8. PowerPC 60x Address to ROM/Flash Address Mapping with
Two 32-bit or One 64-bit Device(s) ........................................................................ 3-19
Table 3-9. Register Summary ................................................................................. 3-30
Table 3-10. ram spd1,ram spd0 and DRAM Type................................................... 3-35
Table 3-11. Block_A/B/C/D Configurations ........................................................... 3-36
Table 3-12. rtest encodings ...................................................................................... 3-44
Table 3-13. ROM Block A Size Encoding .............................................................. 3-46
Table 3-15. Read/Write to ROM/Flash.................................................................... 3-47
Table 3-14. rom_a_rv and rom_b_rv encoding ....................................................... 3-47
Table 3-16. ROM Block B Size Encoding .............................................................. 3-50
Table 3-17. Sizing Addresses .................................................................................. 3-57
Table 3-18. PowerPC 60x Address to DRAM Address Mappings.......................... 3-58
Table 3-19. Syndrome Codes Ordered by Bit in Error ............................................ 3-59
Table 3-20. Single-Bit Errors Ordered by Syndrome Code..................................... 3-60
Table 3-21. PowerPC Data to DRAM Data Mapping ............................................. 3-63
Table 4-1. Universe Register Map ............................................................................ 4-9
Table 5-1. PCI Arbitration Assignments ................................................................... 5-1
Table 5-2. RavenMPIC Interrupt Assignments ........................................................ 5-3
Table 5-3. PIB PCI/ISA Interrupt Assignments ........................................................ 5-6
Table 5-4. Reset Sources and Devices Affected ....................................................... 5-9
Table 5-5. Error Notification and Handling ............................................................ 5-10
Table 5-6. ROM/FLASH Bank Default.................................................................. 5-16
Table A-1. Motorola Computer Group Documents ................................................. A-3
Table A-2. Manufacturers' Documents .................................................................. A-5
Table A-3. Related Specifications ........................................................................ A-10
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