Isa Dma Channels - Motorola MVME2600 Series Reference Manual

Notes:
1. Internally generated by the PIB.
2. Bit 4 of ISA Clock Divisor Register in the PIB must be set to 0 to
support external keyboard interrupt (from the ISASIO device).
3. After a reset, all ISA IRQ interrupt lines default to edge-sensitive
mode.
4. Interrupts from Z8536 and Z85230 devices are externally wire-
ORed. External logic will determine which device to acknowledge
during a pseudo IACK cycle. The Z8536 CIO has higher priority
than the Z85230 ESCC. This IRQ MUST be programmed for level-
sensitive mode.
5. These PCI interrupts are routed to the ISA interrupts by
programming the PRIQ Route Control Registers in the PIB. The
PCI to ISA interrupt assignments in this table are suggested. Each
ISA IRQ to which a PCI interrupt is routed to MUST be
programmed for level-sensitive mode. Use this routing for PCI
interrupts only when the RavenMPIC is either not present or not
used.
6. The RavenMPIC, when present, should be used for these interrupts.

ISA DMA Channels

Refer to Chapter 1 for information on the ISA DMA channels.
ISA DMA Channels
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