Generating Pci Configuration Cycles; Generating Pci Special Cycles - Motorola MVME2600 Series Reference Manual

All I/O accesses must be performed within natural word boundaries. Any
I/O access that is not contained within a natural word boundary will result
in unpredictable operation. For example, an I/O transfer of 4 bytes starting
at address $80000010 is considered a valid transfer. An I/O transfer of 4
bytes starting at address $80000011 is considered an invalid transfer since
it crosses the natural word boundary at address $80000013/$80000014.

Generating PCI Configuration Cycles

Mechanism one (as just described above) is utilized to generate
configuration cycles. Two 32 bit PCI I/O ports at $CF8 and $CFC are used
to access PCI configuration space. One of the four MPC Slave Address
Registers is used to gain access to $CF8 and $CFC. Note that MSADD3 is
initialized at reset to access PCI I/O space with an MPC address of
$80000000.
The resource at $CF8 is a 32 bit configuration address port and is referred
to as the CONFIG_ADDRESS register. The resource at $CFC is a 32 bit
configuration data port and is referred to as the CONFIG_DATA register.
Accessing a PCI functions's configuration port is a two step process;
Write the bus number, physical device number, function number
and register number to the CONFIG_ADDRESS register.
Perform an I/O read from or a write to the CONFIG_DATA register.

Generating PCI Special Cycles

To prime Raven to generate a special cycle, the host processor must write
a 32 bit value to the CONFIG_ADDRESS register. The contents of the
write are defined later in this chapter under the CONFIG_ADDRESS
register definition. After the write to $CF8 has been accomplished, the
next write to the CONFIG_DATA register causes the Raven to generate a
special cycle on the PCI bus. The write data is driven onto AD[31:0]
during the special cycle's data phase.
Functional Description
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