Feature Reporting Register - Motorola MVME2600 Series Reference Manual

Feature Reporting Register

Offset
Bit 3 3 2 2 2
1 0 9 8 7
Name
Operation R
Reset $0
NIRQ
NCPU
VID
$01000
2 2 2 2 2 2 2 1 1 1
6 5 4 3 2 1 0 9 8 7
FEATURE REPORTING
NIRQ
R
$00F
NUMBER OF IRQs. The number of the highest external
IRQ source supported. The IPI, Timer, and Raven
Detected Error interrupts are excluded from this count.
NUMBER OF CPUs. The number of the highest physical
CPU supported. There are two CPUs supported by this
design. CPU #0 and CPU #1.
VERSION ID. Version ID for this interrupt controller.
This value reports what level of the specification is
supported by this implementation. Version level of 02 is
used for the initial release of the MPIC specification.
Raven Interrupt Controller Implementation
1 1 1 1 1 1 1
6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
NCPU
R R
$0 $01
2
VID
R
$02
2-65