Motorola MVME2600 Series Reference Manual page 88

Functional Description
between write cycles, and thereby result in a partially completed write
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cycle. It is recommended that write cycles to write-sensitive non-posted
locations be performed on mod-4 address boundaries.
The Raven has a programmable option to guarantee all PCI write posted
transactions are completed before an MPC initiated read transaction may
be allowed to complete. This option is controlled by the FLBRD bit in the
GSCR register. If this bit is set, all MPC read transactions will be retried
until all posted PCI write transactions have completed. It is recommended
that this option be disabled, and the FLBRD bit be left in the default
(disabled) state.
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