Motorola MVME2600 Series Reference Manual page 100

MATOM bit in the MEREN register is set, the assertion of
this bit will assert MCHK to the master designated by the
MID field in the MERAT register. When the MATOI bit
in the MEREN register is set, the assertion of this bit will
assert an interrupt through the MPIC interrupt controller.
PERR PCI Parity Error. This bit is set when the PCI PERR* pin
is asserted. It may be cleared by writing it to a 1; writing
it to a 0 has no effect. When the PERRM bit in the
MEREN register is set, the assertion of this bit will assert
MCHK to the master designated by the DFLT bit in the
MERAT register. When the PERRI bit in the MEREN
register is set, the assertion of this bit will assert an
interrupt through the MPIC interrupt controller.
SERR PCI System Error. This bit is set when the PCI SERR*
pin is asserted. It may be cleared by writing it to a 1;
writing it to a 0 has no effect. When the SERRM bit in the
MEREN register is set, the assertion of this bit will assert
MCHK to the master designated by the DFLT bit in the
MERAT register. When the SERRI bit in the MEREN
register is set, the assertion of this bit will assert an
interrupt through the MPIC interrupt controller.
SMA PCI Master Signalled Master Abort. This bit is set
when the PCI master signals master abort to terminate a
PCI transaction. It may be cleared by writing it to a 1;
writing it to a 0 has no effect. When the SMAM bit in the
MEREN register is set, the assertion of this bit will assert
MCHK to the master designated by the MID field in the
MERAT register. When the SMAI bit in the MEREN
register is set, the assertion of this bit will assert an
interrupt through the MPIC interrupt controller.
RTA PCI Master Received Target Abort. This bit is set when
the PCI master receives target abort to terminate a PCI
transaction. It may be cleared by writing it to a 1; writing
it to a 0 has no effect. When the RTAM bit in the MEREN
register is set, the assertion of this bit will assert MCHK
to the master designated by the MID field in the MERAT
Registers
2
2-33