Figure 3-4. Data Path For Reads From The Falcon Internal Csrs; Csr Architecture; Programming Model - Motorola MVME2600 Series Reference Manual

Falcon ECC Memory Controller Chip Set

Programming Model

CSR Architecture

3

Figure 3-4. Data Path for Reads from the Falcon Internal CSRs

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3Falcon ECC Memory Controller Chip Set
The CSR (control and status register set) consists of the chip's internal
register set, its test SRAM, and its external register set. The base address
of the CSR is hard coded to the address $FEF80000 (or $FEF90000 if the
SIO pin is low at reset).
Accesses to the CSR are mapped differently depending on whether they
are reads or writes. For reads, CSR data read on the upper half of the data
bus comes from the upper Falcon while CSR data read on the lower half of
the data bus comes from the lower Falcon. (See Figure 3-4.)
MPC60x Master
CSR
Upper FALCON
For writes, internal register or test SRAM data written on the upper half of
the data bus goes to the upper Falcon and is automatically copied by
hardware to the lower Falcon. Internal register or test SRAM data written
on the lower half of the data bus does not go to either Falcon in the pair,
but the access is terminated normally with TA_. (See Figure 3-5.).
CSR
Lower FALCON
1903 9609