Mpc Map Decoders; Table 2-1. Chrp Compliant Memory Map - Motorola MVME2600 Series Reference Manual

MPC Map Decoders

The Raven address decoders have been designed to be as flexible as
possible to provide a wide range of addressing possibilities. There are five
address map decoders in the Raven which determine the MPC bus
addresses to which the Raven will respond: the MPC Register File
Decoder, and four programmable decoders. Table 2-1 shows a typical
CHRP compliant memory map. (Another similar map is shown in Table 1-
3.)

Table 2-1. CHRP Compliant Memory Map

MPC Address
$00000000-$7FFFFFFF
$80000000-$FCFFFFFF
$FD000000-$FDFFFFFFF
$FE000000-$FE7FFFFF
$FE800000-$FEBFFFFF
$FEC00000-$FEF7FFFF
$FEF80000-$FEF8FFFF
$FEF90000-$FEF9FFFF
$FEFA0000-$FEFAFFFF
$FEFB0000-$FEFBFFFF
$FEFC0000-$FEFEFFFF
$FEFF0000-$FEFFFFFF
$FF000000-$FFFFFFFF
The MPC Register File decoder determines the address location of the
Raven's MPC registers from the MPC bus. These registers may be
accessed using only 1-, 2-, 3-, 4-, or 8-byte operations. The location of the
MPC register file is fixed beginning at MPC address $FEFE0000 or
$FEFF0000, depending on the state of the EXT01 bit at the time RST* is
Function
System Memory (2G)
PCI Memory (2G - 48M)
ISA Memory (16M)
Discontiguous PCI IO (8M)
Contiguous PCI IO (4M)
reserved (3.5M)
Falcon 0 Registers (64K)
Falcon 1 Registers (64K)
Falcon 2 Registers (64K)
Falcon 3 Registers (64K)
reserved (192K)
Raven Registers (64K) (EXT00 => 0)
System ROM/Flash (16MB)
Functional Description
2-7
2