Motorola MVME2600 Series Reference Manual page 190

the refresh cycle has completed. This prevents the
generation of illegal cycles to the DRAM when refdis is
updated.
rwcb rwcb, when set, enables the data from the 8 check-bits in
this Falcon to be written and read on the PowerPC 60x
data bus (DH24-31 for upper Falcon, DL24-31 for lower
Falcon). This bit should be cleared for normal system
operation. Note that if test software forces a single-bit
error to a location using this function, the scrubber may
correct the location before the test software gets a chance
to check for the single-bit error at that location. This can
be avoided by disabling scrub writes. Also note that
writing bad check-bits can set the elog bit in the Error
Logger Register. The writing of check-bits causes the
Falcon to perform a read-modify-write to DRAM. If the
location to which check-bits are being written, has a
single- or double-bit error, data in the location may be
altered by the write check-bits operation. To avoid this, it
is recommended that the derc bit also be set while the
rwcb bit is set. A possible sequence for performing read-
write check-bits is as follows:
1. Disable scrub writes by clearing the swen bit if it is set.
2. Stop all DRAM Tester operations by clearing the trun bit.
3. Set the derc and rwcb bits in the Data Control register.
4. Perform the desired read and/or write check-bit operations.
5. Clear the derc and rwcb bits in the Data Control register.
6. Perform the desired testing related to the location/locations that
have had their check-bits altered.
7. Enable scrub writes by setting the swen bit if it was set before.
derc Setting derc to one alters Falcon pair operation as
follows:
Programming Model
3-39
3