Memory Configuration Register; Table 35 Memory Configuration Register - Motorola PPC/CPCI-690 Reference Manual

Maps and Registers

Memory Configuration Register

PPC/CPCI-690
The Memory Configuration Register provides information on memory con-
figuration options.
Table 35: Memory Configuration Register
Base Address: F0000000
Bit Signal
2..0 SDRAM_SIZE
3 FLASH_SIZE
4 SDRAM CAS
7..5 FPGA_REVISION
Offset: 04
16 16
Description
SDRAM configuration
000: Reserved
001: 256 MByte
010: 512 MByte
011: 768 MByte
100: 1 GByte
101: 1.5 GByte
110: 2 GByte
111: Reserved
User flash configuration
0: 32 MByte
1: 64 MByte
SDRAM CAS latency
0: CAS latency is 3
1: CAS latency is 2
FPGA revision status
000: Revision 1.0
Register
Access
r
r
r
r
6 - 13