ECS NEATSX User Manual page 27

The programmable features are as follows:
• Wait State selection
• Selection of DRAM type (256K, or 1MB)
• Interleave and Page Mode operation
• Enäbling/disabling of Shadow RAM
The 215 Chip
The 82C215 Address/Data buffer provides the buffering and
latching between the local CPU address bus and the Peripheral address
bus. It also provides buffering between the local CPU data bus and the
memory data bus (M data bus).
The parity bit generation and error detection logic resides in
the 82C215. The 82C215 is an address/data buffer and is not program­
mable.
Hardware Specifications
21