ECS NEATSX User Manual page 22

Hardware Specifications
Wait States
One of the main things that distinguishes high-speed '286 and
'386 system boards from earlier, slower designs is the way in which
memory access is handled. At a slower clock speed, the common
DRAM memory design had sufficient speed to provide memory ac­
cess for the microprocessor at zero wait states.
With the advent of faster clock speeds, the microprocessor's
speed began to exceed the former configuration's capacity to provide
zero-wait memory access. The page/interleave design is a solution to
this problem that allows for zero-wait operation without requiring the
use of very fast memory chips.
The maximum CPU clock speed, the number of wait states,
and the interleaving factor all depend on the speed of the memory in­
stalled. Listed below are the memory speed requirements for eight
possible system configurations.
16MHz INTERLEAVE:
1.0 WAIT STATE, memory requirement is 100NS
2.1 WAIT STATE, memory requirement is 120NS