ECS NEATSX User Manual page 26

Hardware Specifications
• Optional independent AT bus clock
• CPU interface and bus control
• Programmable command delays and wait state generation
• Port B register
The 812 Chip
The 82C812 is the page/interleave and EMS memory control­
ler for the CS8281 NEATsx CHIPSet. It provides an interleaved mem­
ory subsystem design with page mode operation. It supports up to
8MB of DRAM with combinations of 256Kb and 1Mb DRAMS. The
processor can operate at 16 Mhz with 0.5 to 0.7 wait state memory ac­
cesses using 100ns DRAMs and at 20 Mhz with 80ns DRAMs.
This is possible through a page interleaved memory scheme. A
RAM shadowing feature allows faster execution of EPROM stored
BIOS code by downloading and executing code from RAM. In a DOS
environment, memory above 1MB can be used as EMS memory. The
chip is programmable via the setup program provided.
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