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The chip set consists of the 82C811 CPU/bus controller, the
82C812 page/interleave and EMS controller, the 82C215 address/data
buffer and the 82C206 integrated peripherals controller (IPC). The de
scriptions below are somewhat technical and are provided for those in
terested in the specific functions the individual chips in the set. It is
not necessary to understand this information to use QuickSet to setup
the board.
The 811 Chip
The 82C811 is the bus controller for the CS8281 NEATsx
CHIPSet. It provides synchronization and control signals for all buses.
The 82C811 also provides an independent AT bus clock and allows
for dynamic selection between the processor clock and a user-se
lectable AT bus clock.
Because command delays and wait states are software config
urable, peripheral boards are provided with maximum flexibility. The
chip is programmable via the setup programs provided.
The features are as follows:
Clock generation with software speed selection
Hardware Specifications
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