Input And Output Bits; Plc5, Slc500, And Micrologix (Pccc); Configuration - Banner iVu Plus TG Series Instruction Manual

Ivu plus tg and color gen2 image sensors
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iVu Plus TG and Color Gen2 Image Sensors
In this example, there are only two Blemish sensors in the current inspection. The Blemish3 location will be all zero on the
customizable space. The customizable map had not reserved space for a Match sensor, so Match1 from the inspection will
not be outputted on the custom map.

15.5.4 Input and Output Bits

Writeable Input Bits are inputs to the iVu (outputs from the PLC or HMI). They are used for basic control of the iVu. They are
accessible using function code 6 (Preset Single Register). The same control is also possible using Coils 00001-16, function
code 05 (Force Single Coil).
Table 46: Input Bits: PLC Holding Register 1, also Coils 00001-16
Coil 16
Coil 15
Coil 14
Coil 13
Bit 15
Bit 14
Bit 13
Bit 12
Command
reserved
reserved
reserved
Read-only Input ACK Bits are outputs from the iVu (inputs to the PLC or HMI). They are used to acknowledge each of the
input bits sent from the PLC. For example, if the PLC changes the Trigger bit (from Input Bits, above) from a 0 to a 1, the iVu
changes the Trigger ACK bit from a 0 to a 1 in response. This information is available as Input Registers or Holding
Registers. Use either function code 04 (Read Input Registers) or function code 03 (Read Holding Registers). The same data
can also be read from Inputs (10000) using Modbus function code 02 (Read Input Status).
Table 47: Input ACK Bits: PLC Input Register 1 or Holding Register 1001, also Inputs 10001-16
Input 16
Input 15
Input 14
Input 13
Bit 15
Bit 14
Bit 13
Bit 12
reserved
reserved
reserved
Command
ACK
Read-only Status Bits are outputs from the iVu (inputs to the PLC or HMI). They are used to report the basic status of the
iVu and the last inspection run. This information is available as Input Registers or Holding Registers. Use either function
code 04 (Read Input Registers) or function code 03 (Read Holding Registers). The same data can also be read from Inputs
(10000) using Modbus function code 02 (Read Input Status).
Table 48: Status Bits: PLC Input Register 2 or Holding Register 1002, also Inputs 10017-32
Input 32
Input 31
Input 30
Input 29
Bit 15
Bit 14
Bit 13
Bit 12
Execution
System
Teach
Missed
Error
Error
Error
Trigger

15.6 PLC5, SLC500, and MicroLogix (PCCC)

Allen-Bradley's PLC5, SLC 500, and MicroLogix family of devices uses PCCC communications protocol.
PCCC is also known as EtherNet/IP transport class 3 and uses explicit Read and Write message commands, or EIP
messaging, placed into the ladder logic program, to interface with the Safety Controller.
These PLCs do not support cyclic EtherNet/IP IO data transfer (referred to as EtherNet/IP in this manual). The programming
software used by these PLCs is RSLogix 5 (PLC5) or RSLogix 500 (SLC500 and MicroLogix series).
The iVu supports these PLCs using input and output register arrays.
The Output bits, ACK bits and Input bits bit definitions are the same as defined in
"Input" and "Output" are from the point of view of the PLC.

15.6.1 Configuration

The following images represent a typical configuration.
160
Coil 12
Coil 11
Coil 10
Coil 9
Bit 11
Bit 10
Bit 9
Bit 8
reserved
reserved
reserved
reserved
Input 12
Input 11
Input 10
Input 9
Bit 11
Bit 10
Bit 9
Bit 8
reserved
reserved
reserved
reserved
Input 28
Input 27
Input 26
Input 25
Bit 11
Bit 10
Bit 9
Bit 8
reserved
reserved
reserved
reserved
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Coil 8
Coil 7
Coil 6
Coil 5
Bit 7
Bit 6
Bit 5
Bit 4
reserved
reserved
reserved
reserved
Input 8
Input 7
Input 6
Input 5
Bit 7
Bit 6
Bit 5
Bit 4
reserved
reserved
reserved
reserved
Input 24
Input 23
Input 22
Input 21
Bit 7
Bit 6
Bit 5
Bit 4
Output 3
Output 2
Output 1
reserved
Input and Output Bits
Coil 4
Coil 3
Coil 2
Coil 1
Bit 3
Bit 2
Bit 1
Bit 0
Barcode
Trigger
Teach
Product
models
Latch
Change
only
Input 4
Input 3
Input 2
Input 1
Bit 3
Bit 2
Bit 1
Bit 0
Barcode
Trigger
Teach
Product
models
ACK
Latch
Change
only
ACK
ACK
Input 20
Input 19
Input 18
Input 17
Bit 3
Bit 2
Bit 1
Bit 0
Ready
Read/No
Pass/Fail
Ready
Latch
Read
(p. 160). The terms

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