Reset And Power Supply Supervisor; External Power-On Reset And Power-Down Reset (Npor); System Reset - ST STM32F0 Series Application Note

AN4080
2.2

Reset and power supply supervisor

2.2.1

External power-on reset and power-down reset (NPOR)

To guarantee a proper power-on and power-down reset to the device, the NPOR pin must be
held low until V
state can be exited by putting the NPOR pin in high impedance. The NPOR pin has an
internal pull-up connected to VDDA.
2.2.2

System reset

A system reset sets all registers to their reset values, except the reset flags in the clock
controller CSR register and the registers in the Backup domain. A system reset is generated
when one of the following events occurs:
1. A low level on the NRST pin (external reset).
2. System window watchdog event (WWDG reset).
3. Independent watchdog event (IWDG reset).
4. A software reset (SW reset).
5. Low-power management reset.
6. Option byte loader reset.
7. Power reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR.
The RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In the case of an external reset, the reset is generated while the NRST pin is
asserted low.
Figure 8.
External
reset
Software reset
The SYSRESETREQ bit in Cortex-M0 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the ARMv6-M Architecture
Reference Manual for more details.
is stable or before turning off the supply. When V
DD
Simplified diagram of the reset circuit
V
DD
NRST
Doc ID 023035 Rev 2
Power supplies of the STM32F06xxx family
R
PU
Filter
Pulse
generator
(min 20 μs)
is stable, the reset
DD
System reset
WWDG reset
IWDG reset
Power reset
Software reset
Low-power management reset
Option byte loader reset
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