Figure 7. System Clock Frequency Is Exceeded - ST STM32F0 Series Application Note

AN4055
1. Configure the SYSCLK frequency.
a)
Note: The definition of HSE_VALUE in the stm32f0xx.h file must be modified each time the user
changes the HSE oscillator value.
b)
Figure 7.
c)
d)
e)
f)
g)
Note: In this product the PCLK1 and PCLK2 share the some clock signal, so APB1 prescaler
should always equal APB2 prescaler.
h)
i)
2. If required, enable the I2S clock and configure the I2S clock frequency.
a)
b)
3. Optionally configure the Prefetch buffer.
4. Generate the system_stm32f0xx.c file.
Click the Generate button to automatically generate the system_stm32f0xx.c file in the
same location as the clock tool. It can be displayed to verify the value of the SYSCLK,
SystemCoreClock, and the values of HCLK, PCLK1, PCLK2, Flash access mode, and
other parameters which are defined in the "SetSysClock" function.
5. The system_stm32f0xx.c file must be added to the working project to be built.
If the HSE is used in your application, set its frequency to between 4 MHz and
32 MHz (set it to 32 MHz if a crystal oscillator is used for the STM32F0xx.
If the frequency entered is out of range, an error message is displayed. A valid
frequency must be entered.
Configure the SYSCLK source (PLL, HSE or HSI). If the clock source selection is
invalid (HCLK frequency is too high) the error message in
System clock frequency is exceeded
If PLL is selected as the SYSCLK source, it is necessary to select the source clock
for the PLL (HSE or HSI).
If PLL is selected as the SYSCLK source, configure the main PLL (PLLMUL) and
the PLL division factor (PREDIV) if the HSE is selected as PLL clock source.
Set HCLK prescaler using the AHBPrescaler list box to obtain the desired HCLK
frequency.
Select PCLK1 prescaler settings from the list box to obtain the desired PCLK1
frequency. The TIMCLK frequencies are configured automatically depending on
the PCLK1 prescaler settings.
Select PCLK2 prescaler settings from the list box to obtain the desired PCLK2
frequency. The TIMCLK frequencies are configured automatically depending on
the PCLK2 prescaler settings.
Configure the Flash Latency: after setting the HCLK prescaler, the number of
Flash wait states is configured automatically with the best value (lowest possible
value) which can be modified to any value higher than the best value.
Generate the clock configuration files by clicking on the Generate button.
Select frame width (16 or 32 bits) and specify if the master clock is enabled or not.
Select the Fs from the list box. The Fs value can be 192 kHz, 96 kHz, 48 kHz, 44.1
kHz, 32 kHz, 22.05 kHz, 16 kHz, 11.025 kHz and 8 kHz.
Doc ID 022837 Rev 1
Tutorials
Figure 7 is displayed.
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