Hardware Requirements; Introduction; Clock Scheme For Stm32F0Xx Microcontrollers - ST STM32F0 Series Application Note

AN4055
2.2

Hardware requirements

2.2.1

Introduction

The clock tool is designed to configure the system clocks and generate the
system_stm32f0xx.c file for STM32F0xx microcontrollers.
The system_stm32f0xx.c file is provided as a template system clock configuration file which
can be easily modified to select the corresponding system clock frequency and to configure
the Flash latency.
2.2.2

Clock scheme for STM32F0xx microcontrollers

This section describes the system clock scheme that is dependent on the voltage
requirements (V
clock frequency.
Three different clock sources can be used to drive the system clock (SYSCLK):
1. HSI (8 MHz) oscillator clock
2. HSE (4 MHz to 32 MHz) oscillator clock
3. Main phase-locked loop (PLL) clock with a PLL voltage-controlled oscillator
(PLLVCO) input frequency.
All peripheral clocks are derived from the SYSCLK.
Note: The number of Flash memory wait states (latency) is defined according to the frequency of
the CPU (Cortex-M0):
- Zero wait states if 0 < SYSCLK <= 24 MHz
- One wait state if SYSCLK > 24 MHz
) versus the system clock frequency and Flash latency versus the system
DD
Doc ID 022837 Rev 1
Getting started
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