Reference Design; Description; Clock; Reset - ST STM32F0 Series Application Note

AN4080
7

Reference design

7.1

Description

The reference design shown in
microcontroller running at 48 MHz, that combines the Cortex
with 64 Kbytes of embedded Flash memory and 8 Kbytes of SRAM
For the STM32F061 reference designs, refer to
tailored to any other STM32F05xx or STM32F06xx device with a different package, using
the pin correspondence given in the corresponding datasheet.
7.1.1

Clock

Two clock sources are used for the microcontroller:
● HSE: X1– 8 MHz crystal for the STM32F0xxx microcontroller
●
LSE: X2– 32.768 kHz crystal for the embedded RTC
Refer to
7.1.2

Reset

The reset signal in
●
Reset button (B1)
● Debugging tools via the connector CN1
Refer to
7.1.3

STM32F06xxx power-on reset

The power-on reset signal is active low. It is maintained to V
up resistor. This signal must be provided by the user regulator.
Refer to
7.1.4

Boot mode

The boot option is configured by setting BOOT0 through switch SW1 and option bit
nBOOT1. Refer to
7.1.5

SWD interface

The reference design shows the connection between the STM32F0xxx and a standard SWD
connector. Refer to
Note: It is recommended to connect the reset pin in order to be able to reset the application from
the tool.
7.1.6

Power supply

Refer to
Power supplies of the STM32F06xxx family on page 11
Section 3: Clocks on page
Figure 13 or
Section 1.2.2: System reset on page 8
Section 2.2.1: External power-on reset and power-down reset (NPOR) on page
Section 4: Boot configuration on page
Section 5: Debug management on page
Section 1: Power supplies of the STM32F05xxx family on page 4
Doc ID 023035 Rev 2
Figure 13, introduces the STM32F051, a highly integrated
Figure
15.
Figure 14 is active low. The reset sources include:
or Section 2.2.2: System reset on page 13
Reference design
™
-M0 32-bit RISC CPU core
.
14. These reference designs can be
through an integrated pull-
DDA
18.
19.
or
depending on your configuration.
13.
Section 2:
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