Oracle Netra SPARC T4-1B Service Manual page 50

on an UE, if VEF = 0 and no fatal error is detected in same cycle.
2011-07-03 18:44:14.983 0:7:2>
on a CE, if VEF = VEU = 0 and no fatal or UE is detected in same cycle.
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if the error was a DRAM access UE.
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if the error was a DRAM access CE.
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2011-07-03 18:44:15.486 0:7:2>
1 = 00000034.8647d2e0
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00000005.d21bc0c0
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1 = 00000000.00000800
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1 = dd1676ac.8c18c045
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= 00000000.00000004
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Branch 1 = a8a5f81e.f6411b5a
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for Branch 1 = a8a5f81e.f6411b5a
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Branch 1 = 00000000.00000000
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Branch 1 = 00000000.00000000
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2011-07-03 18:44:16.648 0:7:2>ERROR: POST terminated prematurely. Not
all system components tested.
2011-07-03 18:44:16.786 0:7:2>POST: Return to VBSC
2011-07-03 18:44:16.795 0:7:2>ERROR:
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failures:
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2011-07-03 18:44:17.051 0:7:2>
2011-07-03 18:44:17.145 0:7:2>
2011-07-03 18:44:17.241 0:7:2>END_ERROR
Related Information
"Oracle ILOM Properties That Affect POST Behavior" on page 30
■
"Run POST With Maximum Testing" on page 35
■
"Clear POST-Detected Faults" on page 37
■
40 Netra SPARC T4-1B Server Module Service Manual • June 2012
1 VEC 56
1 DAU 50
1 DAC 46
DRAM Error Address Reg for Branch
Physical Address is
DRAM Error Location Reg for Branch
DRAM Error Syndrome Reg for Branch
DRAM Error Retry Reg for Branch 1
DRAM Error RetrySyndrome 1 Reg for
DRAM Error Retry Syndrome 2 Reg
DRAM Failover Location 0 for
DRAM Failover Location 1 for
POST toplevel status has the following
Node 0 -------------------------------
/SYS/MB/CMP0/BOB0/CH1/D0
/SYS/MB/CMP0/BOB1/CH1/D0
R/W1C Set to 1
R/W1C Set to 1
R/W1C Set to 1