Processor Core; Geodelink Interface Units - Micros Systems Workstation 5 Service Manual

Processor Core

The processor core consists of an integer unit, cache memory subsystem, and
an x87 compatible floating point unit. The integer unit contains the instruction
pipelines and associated logic. The memory subsystem contains the instruction
and data caches, translation look-aside buffers (TLBs) and an interface to the
GeodeLink Interface Units (GLIUs).
The LX800 instruction set is based on a combination of Intel's Pentium
®
AMD K6
™
Geode LX processor specific instructions.

GeodeLink Interface Units

The pair of GeodeLink Interface Units (GLIU0 and GLIU1 in the LX800 block
diagram, Figure 2-3) form the heart of GeodeLink architecture. Each features a
built-in arbiter that enables dynamic allocation of memory bandwidth, with
on-the-fly prioritization.
Internally each GLIU includes seven channels, with channel 0 reserved for the
GLIU itself and not considered a physical port. Together, GLIU0 and GLIU1
make up the internal bus comprised of the GeodeLink architecture. GLIU0
connects to the five modules that require high bandwidth, and GLIU1 connects
to the five low bandwidth modules.
GLIU0 is connected to modules with high-bandwidth requirements:
• CPU Core
• GeodeLink Memory Controller (GLMC)
• Graphics Processor
• Display Controller
• GLIU1 (GeodeLink Interface Unit 1).
GLIU1 is connected to modules with lower bandwidth requirements:
• GeodeLink Control Processor (GLCP)
• Video Input Port
• GeodeLink PCI Bridge
• TFT Controller/Video Output Port (VOP)
• Security Block.
Workstation 5 Field Service Guide
Workstation 5 System Board Technical Descriptions
processor, and the Athlon
LX800 Processor and TFT Controller
™
Floating point unit, and the AMD
®
, the
2-5