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A.1.1 Specifications
Reed-Solomon Codec word
Interleaver
Unique word insertion
Note: The Reed-Solomon implementation conforms to the INTELSAT IESS-308
specification.
A.1.2 Theory of Operation
The Reed-Solomon Codec card works in conjunction with the Viterbi decoder to provide
concatenated convolutional encoding and decoding. The Reed-Solomon Codec block
diagram is shown in Figure A-1. The two main sections of the Codec that will be
discussed in this section are the Reed-Solomon encoder (Section A.1.2.1) and the Reed-
Solomon decoder (Section A.1.2.2).
A.1.2.1 Reed-Solomon Encoder
A block diagram of the Reed-Solomon encoder section is shown in Figure A-2. The
Reed-Solomon encoder section includes the following circuits:
•
•
•
•
•
•
MUXDAT
PARALLEL
JP2
(SERIAL)
SYNCHRONOUS
MUXCLK
SCRAMBLER
JP2
U5
Figure A-2. Reed-Solomon Encoder Section Block Diagram
A–2
8-bit parallel scrambler
Input FIFO
Reed-Solomon Codec
Output First In/First Out (FIFO)
Interleaver
8-bit parallel to 3-bit serial channel reformatter
RS CODEC
INPUT
(ENCODER
FIFO
SECTION)
U6
RS TIMING
CONTROLLER
n = 208
k = 192
t = 8
Modified block interleaving, depth = 4
Per IESS-308 specification
UNIQUE WORD
RAM
INSERTION
INTERLEAVER
U6
U5
INTERLEAVER
ADDRESS
GENERATOR
U5
SDM-9000 Satellite Modem
8 BIT PARALLEL
TXSATDAT
JP2
TO 3 CHANNEL
SERIAL
TXSATCLK
JP2
REFORMATTER
U4
U5
U5
Rev. 4
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