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SDM-9000 Satellite Modem
The 8-bit wide data and clock come from the multiplexer on the interface PCB, and are
sent to the Reed-Solomon encoder section through connector JP1. The data passes
through an 8-bit parallel self-synchronizing scrambler in accordance with IESS-308
Rev. 6B specification. The host software allows the scrambler to be turned on or off at
the front panel, as required by the user. If the scrambler is disabled, the data passes
through the scrambler unaltered.
The data is passed along with dummy check bytes to the input FIFO in the Reed-
Solomon encoder chip. The term n - k = 2t is the total number of check bytes located at
the end of each Reed-Solomon word. This is referred to as the Reed-Solomon overhead.
The Reed-Solomon outer Codec reads the data in blocks of n bytes, and corrects errors.
The letter n represents the total number of bytes in a given block of data out of the
Codec. The letter k represents the number of data bytes in a given block. The output data
is passed to the output FIFO, and then to the block interleaver.
Errors from the Viterbi decoder usually occur in bursts. A block interleaver with a depth
of 4 is used in accordance with the IESS-308 Rev. 6B specification. The interleaver has
the effect of spreading out the errors across several blocks of data instead of
concentrating the errors in a single block. Since there are fewer errors in any given block,
there is a greater chance that the Reed-Solomon decoder can correct the errors on the
receiving end of the satellite link. To allow the decoder to synchronize to the data, four
unique words are inserted in the last two bytes of the last two RS words of the last RS
page of the RS frame (Figure A-3).
Once the data passes through the interleaver, it is fed through a parallel/serial converter
and sent back to the interface PCB. After further processing by the interface PCB, the
data is sent to the modulator PCB.
Rev. 4
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