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No data packing is done on 8- or 16-bit transfers. These modes exist to
support the alignment function, as required. The highest throughput is
achieved with 32-bit transfers.
Use extreme caution when programming start addresses and trans-
fer count to make sure that the DMA channel does not access
unsupported memory, MMR space, scratchpad, or other critical
system resources. Access to illegal memory ranges causes an
exception.
Peripheral DMA Next Descriptor Pointer Register
The value of the peripheral's DMA Next Descriptor Pointer register deter-
mines the lower 16 bits of the descriptor block base address for the next
DMA transfer sequence. After initial configuration of the DMA register
set, this register is updated whenever the DMA channel fetches a new
descriptor block from memory.
Next Descriptor Pointer register.
The LSB of this register must always be 0, because the descriptor list must
be 16-bit aligned. This register is not used for autobuffer mode.
Peripheral DMA Next Descriptor Pointer Register
For MMR assign-
15 14 13 12 11 10
ments, see
Table
9-8.
Figure 9-8. Peripheral DMA Next Descriptor Pointer Register
ADSP-BF535 Blackfin Processor Hardware Reference
Figure 9-8
9
8
0
0
0
0
0
0
0
0
Direct Memory Access
describes the peripheral DMA
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Reset = 0x0000
Next Descriptor
Pointer[15:0]
9-23
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