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DSP Device ID Register (DSPID)
The DSP Device ID register (
and part of the core. The
DSP Device ID Register (DSPID)
RO
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0xFFE0 5000
X
15 14 13 12 11 10
X
Figure 20-16. DSP Device ID Register
DMA Bus Debug Registers
During normal operation, the core has no direct visibility into the DMA
bus. However, the SBIU includes two registers that provide visibility into
the bus and control of it. Additional information about the SBIU is avail-
able in
"Chip Bus Hierarchy" on page
If a DMA channel does not behave as expected, these two registers provide
a debug capability:
• DMA Bus Control Comparator register (
• DMA Bus Address Comparator register (
ADSP-BF535 Blackfin Processor Hardware Reference
DSPID
value is an input to the core.
DSPID
X
X
X
X
X
X
X
X
9
8
7
X
X
X
X
X
X
X
0
Blackfin Processor's Debug
), shown in
Figure
X
X
X
X
X
X
X
6
5
4
3
2
1
0
0
0
0
0
0
0
1
7-1.
DB_CCOMP
DB_ACOMP
20-16, is read-only
Reset = 0x0000 0000
DSPID[7:0]
)
)
20-27
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