Analog Devices ADSP-BF535 Blackfin Hardware Reference Manual page 27

Host Mode Operation ............................................................... 13-13
Outbound Transactions (ADSP-BF535 Processor as PCI
Initiator) .......................................................................... 13-13
Inbound Transactions (ADSP-BF535 Processor as PCI
Target) ............................................................................. 13-14
Outbound Configuration Transactions ...................................... 13-15
Reset Behavior and Control ....................................................... 13-16
Interrupt Behavior and Control ................................................. 13-17
PCI Programming Model .......................................................... 13-18
Bus Operation Ordering ...................................................... 13-18
System MMR Control and Status Registers ................................ 13-19
PCI Bridge Control Register (PCI_CTL) ............................. 13-20
PCI Status Register (PCI_STAT) ......................................... 13-21
PCI Interrupt Controller Register (PCI_ICTL) .................... 13-22
PCI Outbound Memory Base Address Register
(PCI_MBAP) ................................................................... 13-23
PCI Outbound I/O Base Address Register (PCI_IBAP) ........ 13-23
PCI Outbound I/O Configuration Address Register
(PCI_CBAP) .................................................................... 13-24
PCI Inbound Memory Base Address Register
(PCI_TMBAP) ................................................................. 13-25
PCI Inbound I/O Base Address Register (PCI_TIBAP) ......... 13-25
Configuration Space Control and Status Registers ...................... 13-26
PCI Device Memory BAR Mask Register
(PCI_DMBARM) ............................................................. 13-26
PCI Device I/O BAR Mask Register (PCI_DIBARM) .......... 13-27
ADSP-BF535 Blackfin Processor Hardware Reference
Contents
xxvii