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PCI Configuration Interrupt Line Register
(PCI_CFG_IL)
This register, shown in
PCI configuration registers. For more information, see the PCI Local Bus
Specification Rev. 2.2.
PCI Configuration Interrupt Line Register (PCI_CFG_IL)
0xEEFF FF4C
Interrupt Line[7:0]
Figure 13-28. PCI Configuration Interrupt Line Register
PCI Host Memory Control Register (PCI_HMCTL)
This register, shown in
ADSP-BF535 processor memory space are accessible from any initiators
on the PCI bus. There is one-to-one mapping of addresses between the
PCI and the ADSP-BF535 processor in host mode. The PCI core asserts
and claims the transaction for any region indicated as enabled in
DEVSEL
this register. The asynchronous memory access is valid only if the Async
Mem Access Enable bit is set and specifies the size of the accessible Async
Mem window in 64-MB blocks. The SDRAM access size is valid only if
the SDRAM Access Enable bit is set. It specifies the size of the accessible
SDRAM window in 32-MB blocks. This register is valid only in host
mode.
ADSP-BF535 Blackfin Processor Hardware Reference
Figure
13-28, holds the interrupt line from the
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
0
0
0
0
0
0
0
0
Figure
13-29, configures which portions of
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
PCI Bus Interface
Reset = 0x0000 0000
13-43
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