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Asynchronous Memory Bank Control 1 Register (EBIU_AMBCTL1)
0xFFC0 3C08
B3WAT[3:0]
Bank 3 write access time (number of
cycles AWE is held asserted).
0000 - Not supported.
0001 to 1111 - 1 to 15 cycles.
B3RAT[3:0]
Bank 3 read access time (number of
cycles ARE is held asserted).
0000 - Not supported.
0001 to 1111 - 1 to 15 cycles.
B3HT[1:0]
Bank 3 hold time (number of cycles between AWE
or ARE deasserted, and AOE deasserted).
00 - 0 cycles.
01 - 1 cycle.
10 - 2 cycles.
11 - 3 cycles.
B3ST[1:0]
Bank 3 setup time (number of cycles after AOE
asserted, before AWE or ARE asserted).
00 - 4 cycles.
01 - 1 cycle.
10 - 2 cycles.
11 - 3 cycles.
B2WAT[3:0]
Bank 2 write access time (number of
cycles AWE is held asserted).
0000 - Not supported.
0001 to 1111 - 1 to 15 cycles.
B2RAT[3:0]
Bank 2 read access time (number of
cycles ARE is held asserted).
0000 - Not supported.
0001 to 1111 - 1 to 15 cycles.
B2HT[1:0]
Bank 2 hold time (number of cycles between AWE
or ARE deasserted, and AOE deasserted).
00 - 0 cycles.
01 - 1 cycle.
10 - 2 cycles.
11 - 3 cycles.
B2ST[1:0]
Bank 2 setup time (number of cycles after AOE
asserted, before AWE or ARE asserted).
00 - 4 cycles.
01 - 1 cycle.
10 - 2 cycles.
11 - 3 cycles.
Figure 18-5. Asynchronous Memory Bank Control 1 Register
ADSP-BF535 Blackfin Processor Hardware Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
1
1
1
1
1
1
1
15 14 13 12 11 10
9
8
1
1
1
1
1
1
1
1
External Bus Interface Unit
1
1
0
0
0
0
1
0
B3RDYEN
B3RDYPOL
B3TT[1:0]
Bank 3 memory transition time
(number of cycles inserted after
a read access to this bank, and
before a write access to this bank
or a read access to another bank).
00 - 4 cycles for bank transition.
01 - 1 cycle for bank transition.
10 - 2 cycles for bank transition.
11 - 3 cycles for bank transition.
7
6
5
4
3
2
1
0
1
1
0
0
0
0
1
0
B2RDYEN
Bank 2 ARDY enable.
0 - Ignore ARDY for accesses to
1 - After access time countdown,
B2RDYPOL
Bank 2 ARDY polarity.
0 - Transition completes if ARDY
1 - Transaction completes if
B2TT[1:0]
Bank 2 memory transition time
(number of cycles inserted after
a read access to this bank, and
before a write access to this bank
or a read access to another bank).
00 - 4 cycles for bank transition.
01 - 1 cycle for bank transition.
10 - 2 cycles for bank transition.
11 - 3 cycles for bank transition.
Reset = 0xFFC2 FFC2
Bank 3 ARDY enable.
0 - Ignore ARDY for accesses to
this memory bank.
1 - After access time countdown,
use state of ARDY to deter-
mine completion of access.
Bank 3 ARDY polarity.
0 - Transition completes if ARDY
sampled low.
1 - Transaction completes if
ARDY sampled high.
this memory bank.
use state of ARDY to deter-
mine completion of access.
sampled low.
ARDY sampled high.
18-15
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