Table of Contents
Advertisement
• Chapter 18,
Describes the External Bus Interface Unit of the ADSP-BF535 pro-
cessor. The chapter also discusses the asynchronous memory
interface, the SDRAM controller (SDC), related registers, and
SDC configuration and commands.
• Chapter 19,
Describes how to use the processor as part of an overall system. It
includes information about interfacing the ADSP-BF535 processor
to external memory chips, bus timing and latency numbers, sema-
phores, and a discussion of the treatment of unused processor pins.
• Chapter 20,
Describes the Blackfin processor debug functionality, which can be
used for software debugging and complements some services often
found in an operating system.
• Appendix A,
Lists the core memory-mapped registers and their addresses.
• Appendix B,
Lists the system memory-mapped registers and their addresses.
• Appendix C,
Describes test features for the ADSP-BF535 processor; discusses
the JTAG standard, boundary-scan architecture, instruction and
boundary registers, and public instructions.
• Appendix D,
Describes various aspects of the 16-bit data format. The chapter
also describes how to implement a block floating-point format in
software.
• Appendix G,
Contains definitions of terms used in this book, including
acronyms.
ADSP-BF535 Blackfin Processor Hardware Reference
External Bus Interface Unit
System Design
Blackfin Processor's Debug
Blackfin Processor Core MMR Assignments
System MMR Assignments
Test Features
Numeric Formats
Glossary
Preface
xlvii
Advertisement
Table of Contents
