Slave Select Inputs - Analog Devices ADSP-BF535 Blackfin Hardware Reference Manual

Table 10-6. SPI1_FLG Bit Mapping to PFx Pins
Bit Name
0
1 FLS1
2 FLS2
3 FLS3
4 FLS4
5 FLS5
6 FLS6
7 FLS7
8
9 FLG1
10 FLG2
11 FLG3
12 FLG4
13 FLG5
14 FLG6
15 FLG7

Slave Select Inputs

If the SPI is in slave mode,
enabled as a master,
in a multimaster environment. The
ture. When
PSSE = 1
Otherwise,
SPISS
in the Flag Clear register (
( ).
FIO_FLAG_S
ADSP-BF535 Blackfin Processor Hardware Reference
SPI Compatible Port Controllers
Function
Reserved
SPI1SEL1 Enable
SPI1SEL2 Enable
SPI1SEL3 Enable
SPI1SEL4 Enable
SPI1SEL5 Enable
SPI1SEL6 Enable
SPI1SEL7 Enable
Reserved
SPI1SEL1 Value
SPI1SEL2 Value
SPI1SEL3 Value
SPI1SEL4 Value
SPI1SEL5 Value
SPI1SEL6 Value
SPI1SEL7 Value
acts as the slave select input. When
SPISS
can serve as an error detection input for the SPI
SPISS
, the input is the master-mode error input.
SPISS
is ignored. The state of these input pins can be observed
FIO_FLAG_C)
PFx Pin
PF3
PF5
PF7
PF9
PF11
PF13
PF15
PF3
PF5
PF7
PF9
PF11
PF13
PF15
bit in
PSSE SPIx_CTL
or the Flag Set register
enables this fea-
10-13